tree-sitter-systemverilog

Full SystemVerilog IEEE 1800-2023 grammar for tree-sitter.

Differences with tree-sitter-verilog

Pros ##

- Full implementation of the latest SystemVerilog standard (IEEE 1800-2023)
- Robust and reliable: sv-tests results
- Actively maintained
- Implements node fields
- Supports parsing of code snippets (e.g., always block outside of a module)
- Basic preprocessing capabilities
- Thoroughly tested (~3000 tests) including:
- UVM 2.0
- sv-tests
- cva6
- pulp_axi
- basejump_stl
- ucontroller
- Currently used by:
- Emacs verilog-ts-mode
- nvim systemverilog plugin
- helix
- mergiraf

Cons

- Generated parser size is larger (~60MB vs ~45MB)
- Generation of the compiled grammar takes longer (only needs to be done once)

References

- https://en.wikipedia.org/wiki/Verilog
- http://tree-sitter.github.io/tree-sitter/creating-parsers